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cy2544 cy2546 cy2548 quad pll programmable clock generator with spread spectrum cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-12563 rev. *h revised january 8, 2014 quad pll programmable clock generator with spread spectrum features four fully integrated phase locked loops (plls) input frequency range ? external crystal: 8 to 48 mhz for cy2544 and cy2546 ? external reference: 8 to 166 mhz clock reference clock input voltage range ? 2.5 v, 3.0 v, and 3.3 v for cy2548 ? 1.8 v for cy2544 and cy2546 wide operating out put frequency range ? 3 to 166 mhz programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles vdd supply voltage options: ? 2.5 v, 3.0 v, and 3.3 v for cy2544 and cy2548 ? 1.8 v for cy2546 selectable output clock voltages: ? 2.5 v, 3.0 v, and 3.3 v for cy2544 and cy2548 ? 1.8 v for cy2546 frequency select feature with option to select eight different frequencies over nine clock outputs power down, output enable, and ss on/off controls low jitter, high accuracy outputs ability to synthesize nonstandard frequencies with fractional-n capability up to nine clock outputs with programmable drive strength glitch free outputs while frequency switching 24-pin qfn package commercial and industrial temperature ranges benefits multiple high performance plls allow synthesis of unrelated frequencies nonvolatile programming for personalization of pll frequencies, spread spectrum c haracteristics, drive strength, crystal load capacitance, and output frequencies application specific programma ble emi reduction using spread spectrum for clocks programmable plls for system frequency margin tests meets critical timing requirem ents in complex system designs suitability for pc, consumer, portable, and networking applications capable of zero ppm frequency synthesis error uninterrupted system operation during clock frequency switch application compatibility in standard and lo w power systems osc pll1 pll2 pll3 (ss) pll4 (ss) output dividers and drive strength control clk1 clk9 clk8 clk7 clk6 clk5 clk4 clk3 clk2 clkin fs 2 fs 1 fs 0 sson xout xin/ exclkin pd#/oe bank 1 bank 3 bank 2 mux and control logic crossbar switch logic block diagram
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 2 of 17 contents device selection guide .................................................... 3 pinout ................................................................................ 3 pin definitions .................................................................. 3 pinout ................................................................................ 4 pin definitions .................................................................. 5 general description ......................................................... 5 four configurable plls .............................................. 5 input reference clocks .......... .............. .............. ......... 5 multiple power supplies ...... ........................................ 5 output bank settings .................................................. 6 output source selection ............................................. 6 spread spectrum control ............................................ 6 frequency select ........................................................ 6 glitch-free frequency switch ..................................... 6 pd#/oe mode ............................................................. 6 output drive strength .................................................. 6 generic configuration and custom frequency ........... 6 absolute maximum conditions ....................................... 7 recommended operating conditions ............................ 7 dc electrical specifications ............................................ 7 ac electrical specifications ............................................ 9 configuration example for c-c jitter ............................. 9 recommended crystal specification ............................. 9 recommended crystal specification ........................... 10 test and measurement setup ........................................ 10 voltage and timing definitions ..................................... 10 ordering information ...................................................... 11 possible configurations ............................................. 11 ordering code definitions ..... .................................... 12 package drawing and dimensions ............................... 13 acronyms ........................................................................ 14 document conventions ................................................. 14 units of measure ....................................................... 14 document history page ................................................. 15 sales, solutions, and legal information ...................... 17 worldwide sales and design s upport ......... .............. 17 products .................................................................... 17 psoc? solutions ...................................................... 17 cypress developer community ................................. 17 technical support ................. .................................... 17
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 3 of 17 device selection guide device crystal input excklkin input clkin input vdd vdd_clk_bx cy2544 yes 1.8 v lvcmos 2.5 v, 3.0 v, 3.3 v lvcm os 2.5 v, 3.0 v, 3.3 v 2.5 v, 3.0 v, 3.3 v cy2546 yes 1.8 v lvcmos 1.8 v lvcmos 1.8 v 1.8 v cy2548 no 2.5 v, 3.0 v, 3.3 v lvcmos 2.5 v, 3.0 v, 3. 3 v lvcmos 2.5 v, 3.0 v, 3.3 v 2.5 v, 3.0 v, 3.3 v pinout figure 1. 24-pin qfn pinout cy2544 / cy2548 c l k i n clk1 pd#oe cy2544 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 nc clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd clk9 v d d x o u t x i n / e x c l k i n g n d 24ld qfn c l k i n clk1 pd#oe cy2548 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 g n d gnd vdd_clk_b1 nc clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd c l k 9 v d d d n u e x c l k i n g n d 24ld qfn pin definitions cy2544/cy2548 (vdd = 2.5 v, 3.0 v or 3.3 v supply) pin number name i/o description 1 gnd power power supply ground 2 clk1 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 3 vdd_clk_b1 power power supply for bank1, (c lk1, clk2, clk3) outputs: 2.5 v/3.0 v/3.3 v 4 pd#/oe input multifunction programmable pin. output enable or power-down mode 5ncnc no connect 6 clk2 output programmable clock output. output voltage depends on vdd_clk_b 1 voltage 7 gnd power power supply ground 8 clk3/fs0 output/input multifunction programmable pin. programmable clock output clock or frequency select pin. output voltage of clk3 depends on vdd_clk_b 1 voltage 9 oe/fs1 input multifunction programmable pin. output enable or frequency select pin 10 clk4/fs2 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk4 depends on vdd_clk_b 2 voltage
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 4 of 17 11 clk5 output programmable clock output. output voltage depends on vdd_clk_b 2 voltage 12 gnd power power supply ground 13 clk6 output programmable clock output . output voltage depends on vdd_clk_b 2 voltage 14 vdd_clk_b2 power power supply for bank2, (c lk4, clk5, clk6) outputs. 2.5 v/3.0 v/3.3 v 15 clk7/sson output/input multifunction programmable pin. programmable clock output or spread spectrum on/off control input pin . output voltage of clk7 depends on bank3 voltage 16 vdd_clk_b3 power power supply for bank3, (c lk7, clk8, clk9) outputs. 2.5 v/3.0 v/3.3 v 17 clk8 output programmable output clock. output voltage depends on bank3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk9 output programmable clock output . output voltage depends on vdd_clk_b 3 voltage 21 clkin input 2.5 v/3.0 v/3.3 v reference clock input. the signal level of clkin input must track vdd power supply on pin 22. 22 vdd power power supply. 2.5 v/3.0 v/3.3 v 23 xout output crystal output for cy2544 dnu output do not use this pin for cy2548 24 xin/exclkin input crystal input or 1.8 v external clock input for cy2544 exclkin input 2.5 v/3.0 v/3.3 v external clock input for cy2548 pin definitions (continued) cy2544/cy2548 (vdd = 2.5 v, 3.0 v or 3.3 v supply) pin number name i/o description pinout figure 2. 24-pin qfn pinout cy2546 c l k i n clk1 pd#oe cy2546 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 gnd gnd vdd_clk_b1 vdd clk2 o e / f s 1 c l k 3 / f s 0 c l k 4 / f s 2 c l k 5 g n d clk6 vdd_clk_b 2 clk7/sson vdd_clk_b 3 clk8 gnd clk9 v d d x o u t x i n / e x c l k i n g n d 24ld qfn
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 5 of 17 general description four configurable plls the cy2544, cy2548 and cy2546 have four programmable plls that can be used to generate output frequencies ranging from 3 to 166 mhz. the advantage of having four plls is that a single device generates up to four independent frequencies from a single crystal. input reference clocks the input to the cy2544, cy2548 and cy2546 can be either a crystal or a clock signal. the input frequency range for crystal (xin) is 8 mhz to 48 mhz and that for external reference clock (exclkin) is 8 mhz to 166 mhz. the voltage range for the reference clock input of cy2548 is 2.5 v/3.0 v/3.3 v while that for cy2544 and cy2546 is 1.8 v. this gives user an option for this device to be compatible for different input clock voltage levels in the system. there is provision for a secondary reference clock input, clkin with applied frequency range of 8 mhz to 166 mhz. when clkin signal at pin 21 is used as a re ference input to the pll, a valid signal at exclkin (as specified in the ac and dc electrical specification table) must be present for the devices to operate properly. multiple power supplies these devices are designed to operate at internal supply voltage of 1.8 v. in the case of the high voltage part (cy2544/cy2548), an internal regulator is used to generate 1.8 v from the 2.5 v/3.0 v/3.3 v vdd supply voltage at pin 22. for the low pin definitions cy2546 (vdd = 1.8 v supply) pin number name i/o description 1 gnd power power supply ground 2 clk1 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 3 vdd_clk_b1 power power supply for bank1, (c lk1, clk2, clk3) outputs. 1.8 v 4 pd#/oe input multifunction programmable pin. output enable or power down mode 5vddpower power supply. 1.8 v 6 clk2 output programmable clock output. output voltage depends on vdd_clk_b1 voltage 7 gnd power power supply ground 8 clk3/fs0 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk3 depends on vdd_clk_b1 voltage 9 oe/fs1 input multifunction programmable pin. output enable or frequency select pin 10 clk4/fs2 output/input multifunction programmable pin. programmable clock output or frequency select input pin. output voltage of clk4 depends on vdd_clk_b2 voltage 11 clk5 output programmable clock output. output voltage depends on vdd_clk_b2 voltage 12 gnd power power supply ground 13 clk6 output programmable clock output. output voltage depends on vdd_clk_b2 voltage 14 vdd_clk_b2 power power supply for bank2, (c lk4, clk5, clk6) outputs. 1.8 v 15 clk7/sson output/input multifunction programmable pin. programmable clock output or spread spectrum on/off control input pin . output voltage of clk7 depends on vdd_clk_b3 voltage 16 vdd_clk_b3 power power supply for bank3, (c lk7, clk8, clk9) outputs. 1.8 v 17 clk8 output programmable clock output. output voltage depends on vdd_clk_b3 voltage 18 gnd power power supply ground 19 gnd power power supply ground 20 clk9 output programmable clock output. output voltage depends on vdd_clk_b3 voltage 21 clkin input external 1.8 v low voltage reference clock input 22 vdd power power supply. 1.8 v 23 xout output crystal output 24 xin/exclkin input crystal input or 1.8 v external clock input
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 6 of 17 voltage part (cy2546), this internal regulator is bypassed and 1.8 v at vdd pin 22 is directly used. output bank settings there are nine clock outputs grouped in three output driver banks. the bank 1, bank 2, and bank 3 correspond to (clk1, clk2, clk3), (clk4, clk5, clk6), and (clk7, clk8, clk9) respectively. separate power supplies are used for each of these banks and they can be any of 2.5 v, 3.0 v, or 3.3 v for cy2544/cy2548 and 1.8 v for cy2546 giving user multiple choice of output cl ock voltage levels. output source selection these devices have programmable input sources for each of its nine clock outputs (clk1?9). there are six available clock sources for these outputs. these clock sources are: xin/exclkin, clkin, pll1, pll2, pll3, or pll4. output clock source selection is done using f our out of six crossbar switch. thus, any one of these six available clock sources can be arbitrarily selected for the clock outputs. this gives user a flexibility to have up to four independent clock outputs. spread spectrum control two of the four plls (pll3 and pll4) have spread spectrum capability for emi reduction in the system. the device uses a cypress proprietary pll and spread spectrum clock (ssc) technology to synthesize and modulate the frequency of the pll. the spread spectrum feature can be turned on or off using a multifunction control pin (clk7/sson). it can be programmed to either center spread range from 0.125% to 2.50% or down spread range from ?0.25% to ?5.0% with lexmark or linear profile. frequency select there are three multifunction frequency select pins (fs0, fs1 and fs2) that provide an option to select eight different sets of frequencies among each of the four plls. each output has programmable output divider options. glitch-free frequency switch when the frequency select pin (fs) is used to switch frequency, the outputs are glitch-free prov ided frequency is switched using output dividers. this featur e enables uninterrupted system operation while clock frequency is being switched. pd#/oe mode pd#/oe (pin 4) can be programmed to operate as either power down (pd#) or output enable (oe) mode. pd# is a low-true input. if activated it shuts off the entire chip, resulting in minimum power consumption for the device. setting this signal high brings the device in the operational mode with default register settings. when this pin is programmed as output enable (oe), clock outputs can be enabled or disabled using oe (pin 4). individual clock outputs can be programmed to be sensitive to this oe pin. output drive strength the dc drive strength of the individual clock output can be programmed for different values. ta b l e 1 shows the typical rise and fall times for different drive strength settings. generic configuration and custom frequency there is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. the devices, cy2544, cy2548 and cy2546 can be custom programmed to any desired frequ encies and listed features. for customer specific programming, please contact local cypress field application engineer (fae) or sales representative. table 1. output drive strength output drive strength rise/fall time (ns) (typical value) low 6.8 mid low 3.4 mid high 2.0 high 1.0
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 7 of 17 absolute maximum conditions parameter description condition min max unit v dd supply voltage for cy2544/cy2548 ?0.5 4.5 v v dd supply voltage for cy2546 ?0.5 2.6 v v dd_clk_bx output bank supply voltage ?0.5 4.5 v v in input voltage for cy2544/cy2548 relative to v ss ?0.5 v dd + 0.5 v v in input voltage for cy2546 relative to v ss ?0.5 2.2 v t s temperature, storage non functional ?65 +150 c esd hbm esd protection (human body model) jedec eia/jesd22-a114-e 2000 ? v ul-94 flammability rating v-0 at 1/8 in. ? 10 ppm msl moisture sensitivity level 3 recommended oper ating conditions parameter description min typ max unit v dd vdd operating voltage for cy2544/cy2548 2.25 ? 3.60 v v dd vdd operating voltage for cy2546 1.65 1.8 1.95 v v dd_clk_bx output driver voltage for bank 1, 2 and 3 1.65 ? 3.60 v t ac commercial ambient temperature 0?+70c t ai industrial ambient temperature ?40 -- +85 c c load maximum load capacitance ? ? 15 pf t pu power up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter description conditions min typ max unit v ol output low voltage i ol = 2 ma, drive strength = [00] ? ? 0.4 v i ol = 3 ma, drive strength = [01] i ol = 7 ma, drive strength = [10] i ol = 12 ma, drive strength = [11] v oh output high voltage i oh = ?2 ma, drive strength = [00] v dd_clk_bx ? 0.4 ? ? v i oh = ?3 ma, drive strength = [01] i oh = ?7 ma, drive strength = [10] i oh = ?12 ma, drive strength = [11] v il1 input low voltage of pd#/oe, fs0, fs1, fs2 and sson ? ? ? 0.2 v dd v v il2 input low voltage of clkin for cy2544/cy2548 ? ? ? 0.1 v dd v v il3 input low voltage of exclkin for cy2544 ???0.15v
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 8 of 17 v il4 input low voltage of exclkin for cy2548 ? ? ? 0.1 v dd v v il5 input low voltage of clkin, exclkin for cy2546 ? ? ? 0.1 v dd v v ih1 input high voltage of pd#/oe, fs0, fs1, fs2 and sson ? 0.8 v dd ?? v v ih2 input high voltage of clkin for cy2544/cy2548 ? 0.9 v dd ?? v v ih3 input high voltage of exclkin for cy2544 ?1.6?2.2v v ih4 input high voltage of exclkin for cy2548 ? 0.9 v dd ?? v v ih5 input high voltage of clkin, exclkin for cy2546 ? 0.9 v dd ?? v i il1 input low current of pd#/oe and fs1 v il = 0 v ? ? 10 a i ih1 input high current of pd#/oe and fs1 v ih = v dd ??10a i il2 input low current of sson, fs0, and fs2 v il = 0 v (internal pull dn = 160k typ) ??10a i ih2 input high current of sson, fs0, and fs2 v ih = v dd (internal pull dn = 160k typ) 14 ? 36 a r dn pull down resistor of sson, fs0, fs2 and clocks (clk1?clk9) in off-state clock outputs in off-state by setting pd# = low 100 160 250 k ? i dd [1, 2] supply current for cy2546 pd# = high, no load ?20?ma supply current for cy2544/cy2548 pd# = high, no load ?22?ma i dds [1] standby current pd# = low ?3?a c in [1] input capacitance sson, clkin, pd#/oe, fs0, fs1, and fs2 pins ??7pf dc electrical specifications (continued) parameter description conditions min typ max unit notes 1. guaranteed by design but not 100% tested. 2. configuration dependent.
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 9 of 17 ac electrical specifications parameter description conditions min typ max unit f in (crystal) crystal frequency, xin ? 8 ? 48 mhz f in (clock) input clock frequency (clkin or exclkin) ? 8 ? 166 mhz f clk output clock frequency ? 3 ? 166 mhz dc1 output duty cycle, all clocks except ref out duty cycle is defined in figure 4 ; t 1 /t 2 , measured at 50% of v dd _ clk_bx 45 50 55 % dc2 ref out clock duty cycle ref in min 45%, max 55% 40?60% t rf1 [3] output rise/fall time measur ed from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [00] ?6.8?ns t rf2 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [01] ?3.4?ns t rf3 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [10] ?2.0?ns t rf4 [3] output rise/fall time measured from 20% to 80% of v dd _ clk_bx , as shown in figure 5 , c load = 15 pf, drive strength [11] ?1.0?ns t ccj [3,4] cycle-to-cycle jitter (peak) configuration dependent. see configuration example for c-c jitter ? 150 ? ps t lock [3] pll lock time measured from 90% of the applied power supply level ?13ms configuration exam ple for c-c jitter ref. freq. (mhz) clk1 output clk2 output clk3 output clk4 output clk5 output freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) freq. (mhz) c-c jitter typ (ps) 14.3181 8.0 134 166 103 48 92 74.25 81 not used 19.2 74.25 99 166 94 8 91 27 110 48 75 27 48 67 27 109 166 103 74.25 97 not used 48 48 93 27 123 166 137 166 138 8 103 recommended crystal specification for smd package parameter description range 1 range 2 range 3 unit f in crystal frequency 8?14 14?28 28?48 mhz r1 maximum motional resistance (esr) 135 50 30 ? cl parallel load capacitance (see note 3 below) 8?18 8?14 8?12 pf dl(max) maximum crystal drive level 300 300 300 w notes 3. guaranteed by design but not 100% tested. 4. configuration dependent.
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 10 of 17 recommended crystal specification for thru-hole package parameter [5] description range 1 range 2 range 3 unit f in crystal frequency 8?14 14?24 24?32 mhz r1 maximum motional resistance (esr) 90 50 30 ? cl parallel load capacitance (see note 6 below) 8?18 8?12 8?12 pf dl(max) maximum crystal drive level 1000 1000 1000 w test and measurement setup figure 3. test and measurement setup 0.1 ? f v dd outputs c load gnd dut voltage and timing definitions figure 4. duty cycle definition figure 5. rise time = t rf , fall time = t rf clock output v dd_clk_b x 50% of v dd_clk_bx 0v t 1 t 2 clock output t rf t rf v dd_clk_bx 80% of v dd_clk_bx 20% of v dd_clk_bx 0v notes 5. cy2544, cy2548 and cy2546 have internal crystal load capacitance (cl) adjustment feature. 6. guaranteed by design but not 100% tested.
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 11 of 17 some product offerings are factory programmed custom er specific devices with customized part numbers. the possible configurations table shows the available device types, but not complete part numbers. contact your local cypress f ae of sales representative for more information. ordering information part number type [7] package supply voltage operating range pb-free cy2544c field programmable 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2544ct field programmable 24-pin qfn ? tape and reel 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2548c field programmable 24-pin qfn 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2548ct field programmable 24-pin qfn ? tape and reel 2.5 v, 3.0v or 3.3 v commercial, 0 c to 70 c cy2546c field programmable 24-pin qfn 1.8 v commercial, 0 c to 70 c cy2546ct field programmable 24-pin qfn ? tape and reel 1.8 v commercial, 0 c to 70 c cy2544i field programmable 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2544it field programmable 24-pin qfn ? tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548i field programmable 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548it field programmable 24-pin qfn ? tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c CY2546I field programmable 24-pin qfn 1.8 v industrial, -40 c to +85 c CY2546It field programmable 24-pin qfn ? tape and reel 1.8 v industrial, -40 c to +85 c programmer cy3675-clkmaker1 programming kit cy3675-qfn24a socket adapter board, for programming cy2544 and cy2548 [8] possible configurations part number [9] type [7] package supply voltage operating range pb-free cy2544cxxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2544cxxxt factory programmed 24-pin qf n ? tape and reel 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2548cxxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2548cxxxt factory programmed 24-pin qf n ? tape and reel 2.5 v, 3.0 v or 3.3 v commercial, 0 c to 70 c cy2546cxxx factory programmed 24-pin qfn 1.8 v commercial, 0 c to 70 c cy2546cxxxt factory programmed 24-pin qfn ? tape and reel 1.8 v commercial, 0 c to 70 c cy2544ixxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2544ixxxt factory programmed 24-pin qfn ? tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548ixxx factory programmed 24-pin qfn 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c cy2548ixxxt factory programmed 24-pin qfn ? tape and reel 2.5 v, 3.0 v or 3.3 v industrial, -40 c to +85 c CY2546Ixxx factory programmed 24-pin qfn 1.8 v industrial, -40 c to +85 c CY2546Ixxxt factory programmed 24-pin qfn - tape and reel 1.8 v industrial , -40 c to +85 c notes 7. field programmable devices are shipped unprogrammed, and must be programmed before being installed on a board. factory progra mmed devices are shipped fully configured and ready to install on a board. 8. the cy3675-qfn24a cannot be used to program the cy2546. 9. ?xxx? is a variable that denotes a specif ic device configuration. for more details, contact your local cypress fae or cypress sales representative.
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 12 of 17 ordering code definitions x = blank or t blank = tube; t = tape and reel customer specific configuration code temperature grade: x = c or i c = commercial; i = industrial package type: x = blank blank = 24-pin qfn (pb-free) base part number: 254x = 2544 or 2546 or 2548 company id: cy = cypress cy x 254x x x xxx
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 13 of 17 package drawing and dimensions figure 6. 24-pin qfn (4 4 mm) 2.49 2.49 e-pad (subcon punch type package) package outline, 51-85203 51-85203 *d
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 14 of 17 acronyms document conventions units of measure acronym description dl drive level dnu do not use dut device under test eia electronic industries alliance emi electromagnetic interference esd electrostatic discharge fae field application engineer fs frequency select jedec joint electron devices engineering council lvcmos low voltage complimentary metal oxide semiconductor oe output enable osc oscillator pd power down pll phase locked loop ppm parts per million ss spread spectrum ssc spread spectrum clock sson spread spectrum on symbol unit of measure c degree celsius ff femtofarad mhz megahertz ? s microsecond ? w microwatt ma milliampere ms millisecond ns nanosecond ? ohm ppm parts per million pf picofarad ps picosecond v volt w watt
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 15 of 17 document history page document title: cy2544/cy2546/cy2548, quad pll programmable clock generator with spread spectrum document number: 001-12563 revision ecn orig. of change submission date description of change ** 690257 rgl see ecn new data sheet. *a 790516 rgl see ecn separated the pin configuration drawing into two to show the difference between cy2544 and cy2546 pinouts. updated dc electrical specifications : updated test conditions of i ilpdoe parameter (replaced ?internal pull up = 100k typical? with ?no internal pull up?). changed maximum value of i ilpdoe parameter from 10 ? a to 1 ? a. updated test conditions of i ihpdoe parameter (replaced ?internal pull up = 100k typical? with ?no internal pull up?). updated test conditions of i ilsr parameter (replaced ?internal pull down = 100k typical? with ?internal pull down = 160k typical?). updated test conditions of i ihsr parameter (replaced ?internal pull down = 100k typical? with ?internal pull down = 160k typical?). changed the maximum value of i ihsr parameter from 10 ? a to 25 ? a. removed maximum value of i dd parameter (22 ma). added typical value of i dd parameter (15 ma). *b 1508943 rgl / aesa see ecn changed status from preliminary to final. added device selection guide . updated absolute maximum conditions : changed condition of esd hbm parameter from ?mil-std-883, method 3015? to ?jedec eia/jesd22-a114-e?. updated dc electrical specifications : removed v il , v ih , v ilx , v ihx parameters and their details. added v il1 , v ih1 , v il2 , v ih2 , v il3 , v ih3 , v il4 , v ih4 , v il5 , v ih5 parameters and their details. renamed i ilpdoe parameter as i il1 , updated test conditions and changed maximum value of the same parameter from 1 a to 10 a. renamed i ihpdoe parameter as i ih1 , updated test conditions and changed maximum value of the same parameter from 1 a to 10 a. renamed i ilsr parameter as i il2 and changed maximum value of the same parameter from 1 a to 10 a. renamed i ihsr parameter as i ih2 , changed maximum value of the same parameter from 25 a to 36 a and also added minimum value of the same parameter as 14 a. added r dn parameter and its details. changed typical value of i dds value from 50 a to 3 a. updated ac electrical specifications : added t rf1 , t rf2 , t rf3 , t rf4 parameters and their details. renamed t ccj1 parameter as t ccj and added typical value. removed t ltj parameter and its details.
cy2544 cy2546 cy2548 document number: 001-12563 rev. *h page 16 of 17 *b (cont.) 1508943 rgl / aesa see ecn updated configuration example for c-c jitter : removed details of ?long term jitter?. updated details corresponding to ?cycle-to-cycle jitter?. updated recommended crystal specification : removed c0 parameter and its details. updated recommended crystal specification : removed c0 parameter and its details. updated ordering information : deleted generic part numbers. *c 2748211 tsai 08/10/09 post to external web. *d 2764011 cxq 09/15/09 updated ordering information : fixed typo (changed cy2548cxxx and cy2548cxxxt to cy2548ixxx and cy2548ixxxt for industrial temp parts). *e 2899758 kvm 03/26/10 updated ordering information . updated package drawing and dimensions . updated copyright section. *f 2969587 kvm 07/09/2010 minor change: added ?with spread spectrum? in first page title to match spec title on the first page with spec title on the document history page. *g 3115710 bash 12/21/2010 added ordering code definitions . added acronyms and units of measure . *h 4239875 cinm 01/08/2014 updated package drawing and dimensions : spec 51-85203 ? changed revision from *b to *d. updated in new template. completing sunset review. document history page (continued) document title: cy2544/cy2546/cy2548, quad pll programmable clock generator with spread spectrum document number: 001-12563 revision ecn orig. of change submission date description of change
document number: 001-12563 rev. *h revised january 8, 2014 page 17 of 17 all products and company names mentioned in this document may be the trademarks of their respective holders. cy2544 cy2546 cy2548 ? cypress semiconductor corporation, 2007-2014. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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